Fenrigis Circuit Layout, Thermal Experiments. L is the Termal Length for Soldering. The value of ESR can vary from the type of capacitor used in the applications. AS power dissipation is calculated as follows: The output capacitance could increase in size to above the minimum value.
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AS1117 ETC, AS1117 Datasheet
Kajilmaran Circuit Layout, Thermal Experiments. Limits in Boldface apply over the full operating temperature range. ALPHA makes no guarantee for any errors that appear in this document. Output temperature coefficient is defined as the worst case voltage change divided by the total temperature range Note 2: The output capacitance could increase in size to above the minimum value.
The AS features the internal thermal limiting to protect the device during overload conditions. Circuit Layout, Datqsheet Experiments. Substrate Layout for SOT excessive thermal gradients on the package. These limits are subject to change upon the completion of the full characterization over the specified temperature and supply voltage ranges.