74LS93 PDF

Where to use 74LS93? The 74LS93 is a up-counter built using four JK flip-flops. The IC is commonly used by combining mod-2 and mod-8 to form a mod up-counter. The IC is commonly used in counting applications or in divide by 2, divide by 8 or divide by 16 designs. It has two MR Master reset pin which can be used to select the required mode. For normal operation both the pins has to be connected to ground LOW as mentioned in the table below.

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Low Power Consumption. Typically 45 mW High Count Rates. LOW 1. NOTES: a. The Output LOW drive factor is 2. Temperature Ranges. The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 input of the device. To insure proper operation the rise tr and fall time tf of the clock must be less than ns. State changes of the Q outputs do not occur simultaneously because of internal ripple delays.

Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. The Q0 output of each device is designed and specified to drive the rated fan-out plus the CP1 input of the device.

Since the output from the divide-by-two section is not internally connected to the succeeding stages, the devices may be operated in various counting modes. LS90 A. The input count is then applied to the CP1 input and a divide-byten square wave is obtained at output Q0. The first flip-flop is used as a binary element for the divide-by-two function CP0 as the input and Q0 as the output.

The CP1 input is used to obtain binary divide-by-five operation at the Q3 output. LS92 A. The CP0 input receives the incoming count and Q3 produces a symmetrical divide-by-twelve square wave output. The first flip-flop is used as a binary element for the divide-by-two function. The CP1 input is used to obtain divide-by-three operation at the Q1 and Q2 outputs and divide-by-six operation at the Q3 output. The input count pulses are applied to input CP0.

Simultaneous divisions 4, 8, and 16 are performed at the Q1, Q2, and Q3 outputs as shown in the truth table. Simultaneous frequency divisions 2, 4, and 8 are available at the Q1, Q2, and Q3 outputs. Independent use of the first flip-flop is available if the reset function coincides with reset of the 3-bit ripple-through counter.

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